Table 1: Video decode activity of a set-top box chip provides analysis of the effects of clock-tree gating.

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resistor color guide

Triad Magnetics

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This article originally appeared on EE Times Europe.



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This article originally appeared on EE Times Europe.

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THine Electronics


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Networking speeds are growing to keep pace with ever increasing demands for data. Developments in cloud computing, consumer access speeds (Fibre to the Home and LTE) and ubiquitous access (the 3G cell phone) mean that all parts of the communications network, from datacenter to core, have to deal with more data. The major management, switching and routing function blocks in any communication system are generally implemented in ASICs using advanced CMOS processes, today at 40nm with 32nm and 28nm on the horizon. These small geometries enable extremely high-density digital circuits and certainly address the need for realizing digital chips with ever increasing complexity within power and cost budgets. All this concentrated digital processing power naturally presents a huge data I/O requirement, as these digital cores must interface with other chips on the same card, on separate cards in the system or even other systems.

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