ECC19DRYH

Fairchild (ON Semiconductor)

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Another major concern related to the hardware design issue is what level of ECC is sufficient. Since the NAND parts that will be connected to the system cannot be known a priori, the safest solution is to leverage the maximum ECC possible with the memory interface or controller. Using more ECC than required for booting simply improves robustness, with the possible downsides being increased boot time and more complex factory programming procedures.

The challenge with 10GBASE-T is that the early physical layer interface chips (PHYs) have consumed too much power for widespread adoption. The same was true when gigabit Ethernet products were released. The original gigabit chips were roughly 6.5 Watts/ port. With process improvements, chips improved from one generation to the next. The good news with 10GBASET is that these PHYs benefit greatly from the latest manufacturing processes. PHYs are Moore's Law friendly, and the newer process technologies will continue to reduce both the power and cost of the latest 10GBASE-T PHYs.

Raltron

Adeunis

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The challenge with 10GBASE-T is that the early physical layer interface chips (PHYs) have consumed too much power for widespread adoption. The same was true when gigabit Ethernet products were released. The original gigabit chips were roughly 6.5 Watts/ port. With process improvements, chips improved from one generation to the next. The good news with 10GBASET is that these PHYs benefit greatly from the latest manufacturing processes. PHYs are Moore's Law friendly, and the newer process technologies will continue to reduce both the power and cost of the latest 10GBASE-T PHYs.

Compit

Adapteva, Inc.

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It is immediately apparent that such a design must be manufacturable within strict costs limits, which implies everything that conventionally accompanies designs intended for volume production – a manageable bill-of-materials, and operation out-of-the-box with no manual set-up. But the greater challenge is reliability.

ETA-USA
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